FPGA based Optimized Reconfigurable 29 Tap Fir Filter Design using Factored Canonic Signed Digit Technique

Abstract: This paper reveals design and realization of 28 order efficient Finite Impulse Response (FIR) with equiripple characteristics for digital audio signal processing .In this paper the factorized canonical signed digit (FCSD) representation have been used to express the filter coefficients which reduces the design complexity, delay and area of FIR filter. FCSD guarantees the optimality by replacing binary coefficients specified with add and shift operation. FIR filter has been designed on MATLAB using equiripple technique and further the filter is synthesized on XilinxISE9.2 for Spartan 3EXC3S500EFG320-4, VIRTEX2PXC2VP30FF1152-5 FPGA devices. .The FIR filter is simulated I/O of 16 and 32 bit precision on MATLAB platform and FPGA structure. The behavioral simulation is proposed in VHDL model. Using an equiripple method with fixed point data type offers reduction in cost and minimum power consumption. Keywords: FIR, Equiripple, FCSD, Sparten3E XC3S500E, Virtex2P.