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International Journal of Advanced Research in Computer and Communication Engineering
International Journal of Advanced Research in Computer and Communication Engineering A monthly Peer-reviewed & Refereed journal
ISSN Online 2278-1021ISSN Print 2319-5940Since 2012
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← Back to VOLUME 2, ISSUE 12, DECEMBER 2013

FPGA Modelling Of Neuron for Future Artificial Intelligence Applications

KORANI RAVINDER, HAJERA HASAN, IMTHIAZUNNISA BEGUM, DR. P.CHANDRA SEKHAR REDDY M-Tech Phd, Assistant Professor, ECE Department, VIFCET JNTU Hyderabad M-Tech Student [VLSI Design] ECE Department, VIFCET JNTU Hyderabad M-Tech H.O.D, ECE Department, VIFCET JNTU Hyderabad ME M-Tech, Phd Co-ordinator JNTU Hyderabad

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Abstract: This paper presents a digital design of neuron architecture on field-programmable gate array (FPGA). The objective of this project is to translate data from electrochemical sensor signals and process the data with neuron structure on digital hardware. The hardware realization of neural network requires investigation of many design issues relating to signal interfacing and design of a single neuron. Analysis focuses on effect of digital design decisions such as module architecture towards data accuracy and delay. The work touches on analogue to digital interfacing, data structure and digital module design that includes adder, multiplier and multiplier accumulator (MAC). A major component of the algorithm is the design of the activation function. The chosen activation function is the hyperbolic tangent which is approximated by Taylor Series expansion. The neuron is evaluated on an Altera DE2-70 FPGA. The performances are evaluated in terms of functionality, usage of resources and timing analysis. For the data structure, it was demonstrated that increasing the fractional bits will increases the precision. The neuron functionality was demonstrated on digital platform. It was found that less delay were produce by using Carry Look Ahead design compared to Ripple Carry Adder by 25% in the MAC performance.

Keywords: component; formatting; style; styling; insert (key words)

How to Cite:

[1] KORANI RAVINDER, HAJERA HASAN, IMTHIAZUNNISA BEGUM, DR. P.CHANDRA SEKHAR REDDY M-Tech Phd, Assistant Professor, ECE Department, VIFCET JNTU Hyderabad M-Tech Student [VLSI Design] ECE Department, VIFCET JNTU Hyderabad M-Tech H.O.D, ECE Department, VIFCET JNTU Hyderabad ME M-Tech, Phd Co-ordinator JNTU Hyderabad, “FPGA Modelling Of Neuron for Future Artificial Intelligence Applications,” International Journal of Advanced Research in Computer and Communication Engineering (IJARCCE)

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