High Performance Dadda Multiplier Implementation Using High Speed Carry Select Adder

Abstract: Two well known fast multipliers are those presented by Dadda and Wallace. Both multipliers use full adders and half adders in their reduction phase. The half adder does not reduce the number of partial product bits. Therefore minimizing the number of half adders in the multiplier will reduce the complexity. In the modified Wallace tree number of half adders is reduced to 80 percent. In Wallace multiplier the partial products are reduced as soon as possible. Therefore more number of half adders and full adders is required. But in Dadda multiplier reduction is performed whenever necessary. In the final carry propagation path carry select adder is used. A Carry Select Adder using BEC is introduced but it offers some speed penalty. This paper proposes an efficient carry select adder using D Latch.

Keywords: BEC, Dadda, Wallace, Modified Wallace, CSA