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High Performance DCT Implementation Using Reduced Complexity Wallace Multiplier and High Speed Carry Select Adder
ANJU.S, M.SARAVANAN PG Scholar, Department of ECE, SNS College of Technology, Coimbatore, India Assistant Professor, Department of ECE, SNS College of Technology, Coimbatore, India
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Abstract: Discrete cosine Transform are widely used in video and image compression standards. This paper focuses on the implementation of Discrete Cosine Transform DCT) using reduced complexity Wallace multiplier and high speed carry select adder. Wallace Multipliers basically use full adders and half adders in their reduction phase. The number of partial product bits are not being reduced by the half adder. Therefore minimizing the number of half adders in the multiplier will reduce the complexity. In the modified Wallace tree number of half adders are reduced to 80 percent. Inorder to improve the speed a carry select adder with D Latch is being used in the final carry propagation path. The design entry is done in Verilog and simulated using ModelSim 6.1.
Keywords: BEC, Wallace, Modified Wallace, CSA
Keywords: BEC, Wallace, Modified Wallace, CSA
How to Cite:
[1] ANJU.S, M.SARAVANAN PG Scholar, Department of ECE, SNS College of Technology, Coimbatore, India Assistant Professor, Department of ECE, SNS College of Technology, Coimbatore, India , “High Performance DCT Implementation Using Reduced Complexity Wallace Multiplier and High Speed Carry Select Adder,” International Journal of Advanced Research in Computer and Communication Engineering (IJARCCE)
This work is licensed under a Creative Commons Attribution 4.0 International License.