Implementation of Low Power and Area Efficient Shift Register by Register Reusing

Abstract: As the Word length of the shift register increases, the area and power consumption also increases. This paper proposes a low power and area efficient shift register by register reusing. In this system the multiple non-overlap delayed pulsed clock signals is used which timing problem between pulsed latches. The small number of pulsed clock signals used by grouping the latches to several subshift registers. Moreover, the similar functional operation of Register Reusing has been explained by using the Twisted Ring counter.

Keywords: Pulsed latches, pulsed Generator, Twisted Ring counter (TRC), Sub Shift Registers.