Implementation of reversible vedic multiplier for low latency and reduced resources utilization applications

Abstract: Reversible computation is an emerging area of research, having applications in nanotechnology, low power design and quantum computing. It is proved that reversible logic has zero internal power dissipation. Multiplication plays an important role in the processors. It is one of the basic arithmetic operations and it requires more hardware resources and processing time than the other arithmetic operations. Vedic mathematic is the ancient Indian system of mathematic. It has a unique technique of calculations based on 16 Sutras. The multiplication sutra between these 16 sutras is the Urdhva Tiryakbhyam sutra which means vertical and crosswise. In this paper it is used for designing a low latency and reduced resources 4*4 Vedic multiplier. The important parameters in designing reversible logic circuits like no of flipflops,no of LUT’s , Total Equivalent gate count for design are estimated and reported for our proposed reversible Vedic multiplier.

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