Low power wallace and dadda multiplier based on CLRCL full adder

Abstract: Multiplication is one of the most critical arithmetic operation, which is extensively used in many VLSI systems such as application specific based digital signal processor architectures and microprocessor. Multipliers are the major source of power dissipation in the VLSI systems. By reducing the power consumption of the multipliers the power consumption of the VLSI system can be reduced. This paper presents the CLRCL full adder based 4*4 Wallace and Dadda multipliers. The CLRCL full adder has only ten transistors which is less in number when compared with conventional full adders which is used to design these multipliers. Designing Wallace and Dadda multiplier by using CLRCL full adder will reduce the transistor count and power consumption. The proposed design is simulated using 0.12μm.

Keywords: Full adder, multiplier, Power consumption, Wallace multiplier, Dadda multiplier