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This work is licensed under a Creative Commons Attribution 4.0 International License.
Novel Design of Four-Bit Reversible Numerical Comparator
PALLAVI MALL , A.G.RAO, H.P.SHUKLA NIELIT, Gorakhpur Centre Gorakhpur, India NIELIT, Gorakhpur Centre Gorakhpur, India NIELIT, Gorakhpur Centre Gorakhpur, India
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Abstract: In this paper, a new four bit reversible comparator circuit has been designed and was found that the proposed design is better in terms of no. of garbage outputs, no. of reversible logic gates used and no. of constants inputs than previous design. Reversible Logic Technology is becoming a very popular technology in the field of Nano-
using VHDL and Active-HDL 7.1 Version.
Keywords: Reversible Logic Gate; Quantum Cost; Garbage Output; Constant Input; Comparator.
using VHDL and Active-HDL 7.1 Version.
Keywords: Reversible Logic Gate; Quantum Cost; Garbage Output; Constant Input; Comparator.
How to Cite:
[1] PALLAVI MALL , A.G.RAO, H.P.SHUKLA NIELIT, Gorakhpur Centre Gorakhpur, India NIELIT, Gorakhpur Centre Gorakhpur, India NIELIT, Gorakhpur Centre Gorakhpur, India, โNovel Design of Four-Bit Reversible Numerical Comparator,โ International Journal of Advanced Research in Computer and Communication Engineering (IJARCCE)
This work is licensed under a Creative Commons Attribution 4.0 International License.