Performance Analysis of RCA – CSKA and CSA with Proposed Adder Cell

Abstract: In this work, 32-bit ripple carry adder, Carry Skip adder and Carry Save adder circuits have been proposed with ten transistor based one bit full adder. Lower area and high performance chips are the most important parameters in today`s VLSI designs. The minimum power consumption target and lower area can be meet by decreasing the hardware size and which is achieved by reducing the transistor count. Therefore the three designed circuits have been simulated by using Microwind 3.1 VLSI CAD tool. Various parameters such as area, power dissipation, propagation delay and PDP have been determined from layouts of feature size 90nm and 65nm technologies. The adder circuits have been analyzed using BSIM 4 parameter analyzer. Finally the simulation results were compared with conventional adders in terms of total power consumption, delay, area and power delay product.

Keywords: CMOS; Conventional Full Adder; Low Power design; 32-bit RCA;32-bit CSKA; 32-bit CSA.