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International Journal of Advanced Research in Computer and Communication Engineering A monthly Peer-reviewed & Refereed journal
ISSN Online 2278-1021ISSN Print 2319-5940Since 2012
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← Back to VOLUME 5, ISSUE 3, MARCH 2016

Performance Evaluation of Different Multipliers in VLSI using VHDL

M. Aravind Kumar, O. Ranga Rao, M. Dileep, C V Pradeep Kumar Reddy, K.P. Mani

DOI: 10.17148/IJARCCE.2016.5302

Abstract: Multiplier modules are common to many DSP applications. The fastest types of multipliers are parallel multipliers. Among these, the Array multiplier is the basic one. However, they suffer from more propagation delay. Hence, where regularity, high performance and low power are primary concerns, Booth multipliers tend to be the primary choice. Booth multipliers allow the operation on signed operands in 2's-complement which are derived from array multipliers where each bit in a partial product line an encoding scheme is used to determine whether the bit is positive, negative or zero. The Modified Booth algorithm achieves a major performance improvement through radix-4 encoding. In this algorithm each partial product line operates on 2 bits at a time, thereby reducing the total number of the partial products. This is particularly true for operands using 16 bits or more.



Keywords: Array multiplier, parallel multiplier, propagation delay, VHDL, LUT, DSP block, utilization and twiddle f- actors.

How to Cite:

[1] M. Aravind Kumar, O. Ranga Rao, M. Dileep, C V Pradeep Kumar Reddy, K.P. Mani, “Performance Evaluation of Different Multipliers in VLSI using VHDL,” International Journal of Advanced Research in Computer and Communication Engineering (IJARCCE), DOI: 10.17148/IJARCCE.2016.5302