Performance Study of Reed Solomon Code with Effective Error correction and Minimum Area Constraint on FPGA

Abstract: In wireless, satellite communication systems reducing error rate is crucial. High bit error rates of the wireless communication system need using numerous committals to writing ways on the info transferred. Channel committal to writing for error detection and correction helps the communication system designers to cut back the consequences of a loud channel. The aim of this paper is to review and investigate the performance of Reed-Solomon code that's wont to decode the info stream in electronic communication. This paper presents a style on Reed Solomon Code for Wi-Max Network. The implementation is predicated on Berlekamp Massey, Forney and Chain formula. The 802.16 network customary recommends the use of Reed-Solomon code RS that is enforced and mentioned during this paper. It�s targeted to be applied during a forward error correction system supported 802.16 network customary to boost the general performance of the system.

Keywords: Reed Solomon, Generator polynomial, Syndrome calculator, FPGA.