Power and Area Efficient High Speed Squaring Circuit using Vedic Mathematical Techniques

Abstract: Vedic Mathematics is an ancient practice which has a unique procedures based on the sixteen Sutras dealing with the different branches of mathematics viz., arithmetic, calculus, algebra, geometry etc. The interest for high speed processing has been growing as an effect of wide computer processing applications. Very efficient math operations are important to accomplish the desired performance in several real-time systems such as Cryptography and Image Processing. Squaring is one of the key arithmetic operations in many applications like finding the transforms or the inverse transforms in signal processing and the development of fast squaring circuit has been a subject of interest over decades. The key requirements for many applications are to reduce the time delay and power consumption for many applications. In this paper, we have proposed power and area efficient fast squaring circuit using Vedic Multiplier and the proposed dsign is compared with the Vedic Multiplier and squaring circuits. The functionality of this circuit is verified and performance evaluation is done using Xilinx ISE design Suite 14.4 on target device xc5vlx20t-2ff363.

Keywords: Vedic Mathematics, Vedic multiplier, Squaring Circuit, Carry Save Adder, Shifter, Combinational Path Delay, Slices, Digital signal processors.