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International Journal of Advanced Research in Computer and Communication Engineering A monthly Peer-reviewed & Refereed journal
ISSN Online 2278-1021ISSN Print 2319-5940Since 2012
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← Back to VOLUME 4, ISSUE 3, MARCH 2015

Single-ElectronTransistor Logic for High Reliability of Moore’s Law and Low Power VLSI

P. Vidya Sekhar, M. Saran Chowdary, A.Vamsidhar, P.V.S.Sri Ram, N.Venkateswarulu

DOI: 10.17148/IJARCCE.2015.4399

Abstract: The observation made in 1965 by Gordon Moore, co-founder of Intel, that the number of transistors that are embedded per square inch on integrated circuits had doubled every 18 months since the integrated circuit was invented. But as per latest trends in VLSI the channel width cannot be less than equal to 18nm, so Moore�s law came to deadline in recent years. This can be avoided by using SET whose channel width ~1nm. Recent research in SET gives new ideas which are going to revolutionise the random access memory and digital data storage technologies too. Single-electron transistor (SET) is a key element of current research area of nanotechnology which can offer low power consumption and high operating speed. The single electron transistor is a new type of switching device that uses controlled electron tunnelling to amplify current.



Keywords: VLSI, SET, Moore's Law, Island, Tunnelling effect.

How to Cite:

[1] P. Vidya Sekhar, M. Saran Chowdary, A.Vamsidhar, P.V.S.Sri Ram, N.Venkateswarulu, “Single-ElectronTransistor Logic for High Reliability of Moore’s Law and Low Power VLSI,” International Journal of Advanced Research in Computer and Communication Engineering (IJARCCE), DOI: 10.17148/IJARCCE.2015.4399