Abstract: In today’s digital signal processing (DSP) world, there is often a need to convert signals between time and frequency domains. FAST Fourier transform (FFT) is a widely used and popular circuit design technique in the communication fields. It is a reduced form of discrete Fourier transform (DFT) in mathematics nature. For this reason, the fast Fourier transform (FFT) has become one of the most important algorithms in the field. The FFT has played a significant role in digital signal processing field, especially in the advanced communication systems, such as orthogonal frequency division multiplexing (OFDM) and asymmetric digital subscriber line. All these systems require that the FFT computation must be high throughput and low latency. Therefore, designing a high-performance FFT circuit is an efficient solution to the abovementioned problems. The proposed architecture is an efficient combined single-path delay commutator-feedback (SDC-SDF) radix-2 pipelined fast Fourier transform architecture, which includes log2N−1 SDC stages and 1 SDF stage. The SDC processing engine is proposed to achieve 100% hardware resource utilization by sharing the common arithmetic resource in the time-multiplexed approach, including both adders and multipliers. Thus, the required number of complex multipliers is reduced to log4N−0.5, compared with log2N−1 for the other radix-2 SDC/SDF architectures. In addition, the proposed architecture requires roughly minimum number of complex adders log2 N+1 and complex delay memory 2N+1.5log2N−1.5. Standard FPGA Flow is adapted to implement this project. i.e., right from specification to bit file generation, which is going to be programmed on FPGA. The Work chosen for this project is to Implement Pipelined FFT Architecture using Verilog HD and implemented on the FPGA Spartan6.
Keywords: FFT, SDF, SDC, FPGA.
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DOI:
10.17148/IJARCCE.2023.124170
