Abstract: This research paper presents the design and implementation of a 32-bit single-cycle RISC-V (RV32I) processor using Verilog HDL, targeting FPGA-based deployment for educational and embedded system applications. RISC-V, an open-standard instruction set architecture (ISA), provides an alternative to proprietary architectures by offering flexibility, scalability, and ease of implementation. The processor is structured around the fundamental stages of instruction execution, including instruction fetch, decode, execute, memory access, and write-back. To enhance performance, a five-stage pipelining approach is incorporated, reducing execution time per instruction while maintaining design simplicity. Key modules implemented in the processor architecture include the program counter, instruction memory, register file, arithmetic logic unit (ALU), data memory, pipeline registers, multiplexers, and a hazard detection unit to address data and control hazards. The entire design is synthesized and validated using FPGA platforms such as Xilinx Spartan-6 and Spartan-3E, with functional verification conducted through Xilinx ISE and Vivado simulation tools. The processor achieves a maximum operating frequency of 32 MHz, with an estimated power consumption of 7.9 mW, as analyzed using the Xilinx Power Analyzer. The implementation demonstrates the feasibility of a low-cost, fully synthesizable RISC-V processor, offering an efficient and scalable solution for embedded system applications. Furthermore, the development framework includes assembling tools and automated test suites to validate the processor’s functionality. This work contributes to the advancement of open-source processor design, providing insights into the hardware realization of RISC-V and establishing a foundation for future research into more complex architectures.
Keywords: RISC-V, Instruction Set Architecture , Verilog, Simulation.
|
DOI:
10.17148/IJARCCE.2025.14143
