Abstract: SRAM, or Static Random Access Memory, is one of the fundamental elements of the digital world. In general, it uses a tremendous quantity of energy. A lot of SRAM research is thus being done in the areas of power dispersion, RAM chip size, and supply voltage requirements. This work considers SRAM analysis for low power applications in terms of Static Distortion Margin, The Information Retention Voltage, which is Read Margin (RM), and Write Margin (WM). One of the most crucial factors in memory design is static noise margin (SNM), which has an impact on both read and write tolerance. The threshold voltages of the SRAM cell's negative oxide metal transistor (NMOS) and positive metal oxide semiconductor (PMOS) components are correlated with SNM. High Write and Read Snr Margin are also major design obstacles. The challenge of the 6T SRAM project using 180nm, 90nm and 45nm technologies at Cadence Virtuoso is to address the scaling challenges of SRAM designs and explore the possibilities offered by different technology nodes. The focus is on optimizing the performance and energy efficiency of the 6T SRAM cells considering the effects of scaling and process variation. The purpose of this project is to analyze the trade-offs between power consumption, access time, and stability at each technology node, identify optimal design configurations, and develop guidelines for efficient and reliable 6T SRAM design. By leveraging Cadence Virtuoso's capabilities, this project aims to provide valuable insight into the development of robust, high performance SRAM cells in 180nm, 90nm and 45nm technologies.
Keywords: Noise Margin, Read Margin, SRAM, 6T-SRAM, Virtuoso, Write Margin
|
DOI:
10.17148/IJARCCE.2023.126100
