Abstract: One of the most important functional components in any processor is the Multiply-Accumulator (MAC). These functional blocks are currently employed in Fast Fourier Transform (FFT), Finite Impulse Response (FIR) filtering, convolution, and a variety of other DSP and DIP applications. Multiplication and addition are two basic operations that, when compared to other functional blocks, require more hardware resources and computing time. Speed of the multiplier and adder blocks determines the speed of the processor. In this work, a fixed-point power-efficient multiplier and an optimal delay adder block for 2D image convolution have been built and integrated into the MAC unit. Effective multiplication and accumulation units are required due to the demand for high-performance computing systems. The performance of the entire system can be greatly impacted by MAC unit delays, too. In order to find methods that efficiently reduce MAC unit delay, this study compares several adder and multiplier architectures using Xilinx software to handle this difficulty. The results of this study can help researchers and system designers choose optimal designs that balance performance and resource usage, which will ultimately result in increased efficiency and accelerated processing in a variety of computational domains.
Keywords: MAC, Delay, Adders, Multipliers.
|
DOI:
10.17148/IJARCCE.2023.126109
