Abstract: In the field of VLSI research in electronic circuitry. Memory is the basic demand of most electronic devices. These memory components are designed specifically using a CMOS transistor. When we talk about CMOS power, the area and speed of each transistor is a big deal. But we know there is a trade-off between these three things. Engineers and researchers are still working on these questions. Various methods have been used to reduce water leakage within the designed circle. As a result, the praise capacity in the SRAM cell is reduced and it works better. The computing power in the SRAM bitcell is reduced and its performance is better. The designed SRAM bitcell showed nearly 3 times the purging power of the SRAM 6T bitcell. Read and write times access to SRAM bitcell intended to increase and decrease volume. RAM is used as main memory for small value devices that do not have a cache. Therefore, the construction of memory using an optimized SRAM cell in terms of process parameters, i.e. power consumption, quantity, area and delay, is a domain of concern. Critical analysis and the same are presented in a functional way. The SRAM 6T to 10T was found to have better performance in terms of power consumption and power model, but has a higher access time than other existing SRAM components when compared to the results obtained in mode CMOS with Micro wind Tools.

Keywords: VLSI, Memory, SRAM, DRAM, Power Consumption, Power Reduction, Power Dissipation, CMOS Technology, Delay.

PDF | DOI: 10.17148/IJARCCE.2021.101112

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