Design and Analysis of a Low-Power High- Speed 32-bit ALU Using Optimized CMOS Architecture

Abstract: With continuous scaling of CMOS technology and increasing demand for energy-efficient computing systems, the design of high-performance and low-power arithmetic circuits has become a critical challenge in Very Large-Scale Integration (VLSI). The Arithmetic Logic Unit (ALU) is one of the most frequently utilized components in microprocessors, digital signal processors, and embedded systems. Its power consumption and delay significantly influence overall system performance. This paper presents the design, implementation, and analysis of a 32-bit low- power high-speed ALU using an optimized Carry Lookahead Adder (CLA) architecture in 45nm CMOS technology. The proposed design incorporates transistor sizing optimization, clock gating, and multi-threshold CMOS techniques to minimize dynamic and leakage power. Performance evaluation is carried out in terms of propagation delay, average power consumption, and Power-Delay Product (PDP). Comparative analysis with a conventional Ripple Carry Adder (RCA)-based ALU demonstrates significant improvements in speed and energy efficiency. The proposed architecture is suitable for next-generation low-power computing applications.

Keywords: VLSI, CMOS, Low-Power Design, ALU, Carry Lookahead Adder, Power-Delay Product, 45nm Technology, Clock Gating.