Design and FPGA Implementation of a Low- Power Dynamic Clock-Gated Data Processing Unit

Abstract: Power consumption has become a critical design constraint in modern digital systems, particularly in battery-operated embedded devices, Internet of Things (IoT) applications, and FPGA-based computing platforms. Clock networks contribute a significant portion of the total dynamic power consumption due to continuous switching activity, even when functional modules remain idle. This paper presents the design and FPGA implementation of a Low-Power Dynamic Clock-Gated Data Processing Unit (DPU) using Verilog HDL. The proposed architecture incorporates a dynamic clock-gating mechanism that selectively disables clock signals to inactive processing blocks, thereby reducing unnecessary switching activity and minimizing power dissipation. The Data Processing Unit integrates arithmetic, logical, and data manipulation functions controlled through a centralized control unit and intelligent clock-gating circuitry. The design is modeled at the Register Transfer Level (RTL) and synthesized for FPGA implementation. Functional verification is performed using comprehensive simulation scenarios to validate the correctness of all processing operations and clock-gating behavior. Experimental results indicate that the proposed architecture achieves approximately 35–45% reduction in dynamic power consumption compared to conventional non- clock-gated designs while maintaining equivalent computational performance. Furthermore, the design operates at a maximum clock frequency of 180 MHz with less than 60 FPGA logic elements utilized. The combination of low power consumption, reduced switching activity, and efficient hardware utilization demonstrates the effectiveness of the proposed dynamic clock-gated DPU for energy-efficient FPGA-based digital systems and embedded applications.

Keywords: Dynamic Clock Gating, Data Processing Unit, FPGA Implementation, Low-Power Design, Verilog HDL, Energy-Efficient Computing.