Abstract: Vedic Mathematics is an ancient Indian mathematical system known for its unique and efficient methods of computation. This paper presents the design of an 8-bit multiplier that makes use of the Nikhilam Sutra (NS) to create a fast constant coefficient (with 0xFF) and the Yavadunam Sutra (YS) to create a fast squarer which accepts inputs between 0xF0 and 0xFF. The top module decides which module to use based on the input values and makes use of IP Core for standard multiplication. The designs are implemented in Verilog and implemented in Xilinx Vivado, making use of the Atrix-7 FPGA board. The results show improvement in the NS and YS module, in terms of utilization, power consumption, and path delay. The top module, however, suffers from overheads due to multiplexing and comparisons, which offset the performance gains observed.
Keywords: Vedic, Multipliers, Yavadunam, Nikhilam, Verilog, DSP
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DOI:
10.17148/IJARCCE.2024.13613
