Abstract: Modern non-volatile memories, especially Multi-Level Cell (MLC) Flash and ReRAM, suffer from asymmetric and limited-magnitude errors that significantly degrade reliability. Traditional SEC–DED codes fail to correct multi-level and adjacent magnitude errors efficiently. This paper presents the design and FPGA implementation of Limited-Magnitude Error Correction Codes (LM-ECC) for MLC memory systems. The architecture includes SL-SEC, ML-SEC, and IP-SEC-DAEC designs synthesized on Xilinx FPGA. Comparative results demonstrate that the proposed design achieves lower area, reduced power consumption, and improved error-correction efficiency compared to existing techniques. The implementation is validated using Xilinx Vivado with optimized power, timing, and area metrics.
Keywords: MLC Memory, Error Correction Codes, Limited Magnitude Errors, SEC-DAEC, FPGA Implementation, Xilinx, Digital Design.
Downloads:
|
DOI:
10.17148/IJARCCE.2025.1411146
[1] Prof. Rohith H S, Asif S Nadaf, Suraj S R, Venkatesh R, MD Farhan Kotur, "FPGA IMPLEMENTATION OF ADVANCED ERROR DETECTION AND CORRECTION TECHNIQUES FOR MULTI CELL MEMORIES," International Journal of Advanced Research in Computer and Communication Engineering (IJARCCE), DOI: 10.17148/IJARCCE.2025.1411146
