Abstract: High-speed arithmetic units are a critical requirement in modern digital signal processing systems and general-purpose processors. Among these units, multipliers and multiplier-and-accumulator (MAC) blocks significantly influence overall system performance. This paper presents a novel MAC architecture based on the Radix-4 Modified Booth multiplication algorithm, implemented on a Xilinx FPGA platform. The proposed design integrates multiplication and accumulation operations using an efficient hybrid adder structure, resulting in improved computational speed and reduced hardware complexity. The Modified Booth encoding technique minimizes the number of generated partial products by approximately half compared to conventional multiplication methods, thereby enhancing processing efficiency. By optimizing partial product generation and accumulation, the proposed architecture achieves faster arithmetic operations, making it suitable for high-performance DSP applications.
Keywords: Radix-4 Booth Multiplier, Multiplier-Accumulator (MAC), Modified Booth Encoding, FPGA Implementation, Digital Signal Processing, Hybrid Adder.
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DOI:
10.17148/IJARCCE.2025.1412129
[1] Brunda A, Chakravarthi M N, Madhushree S, Dr. Samyuktha S, "FPGA IMPLEMENTATION OF BOOTH MULTIPLIER USING RADIX-4 ALGORITHM," International Journal of Advanced Research in Computer and Communication Engineering (IJARCCE), DOI: 10.17148/IJARCCE.2025.1412129
