International Journal of Advanced Research in Computer and Communication Engineering

Abstract: In the era of high-performance computing and miniaturized electronic systems, the demand for high-speed, low- power, and area-efficient arithmetic units has increased significantly. Among all arithmetic operations, multiplication plays a vital role in determining overall system performance, especially in digital signal processing, cryptography, image processing, and embedded systems. Conventional multiplier architectures such as array multipliers, Booth multipliers, and Wallace tree multipliers often suffer from high propagation delay, increased power consumption, and larger silicon area when scaled to higher bit-width operations.

To address these limitations, this paper presents the design and VLSI implementation of a 64-bit multiplier based on the Urdhva Tiryakbhayam (UT) Sutra of Vedic Mathematics. The UT algorithm, meaning “Vertically and Crosswise,” enables parallel generation of partial products, resulting in reduced computation delay and improved throughput. The proposed architecture is designed using Verilog HDL and follows a hierarchical approach by decomposing large-bit multiplication into smaller modular blocks. Functional verification is carried out through extensive simulation, followed by synthesis and physical implementation using standard VLSI design flow.
Post-synthesis and post-layout analysis demonstrate that the UT-based multiplier achieves superior speed performance while maintaining competitive power consumption and area utilization when compared with conventional multiplier architectures. The results validate the effectiveness of integrating Vedic mathematical principles with modern VLSI methodologies for high- performance arithmetic circuit design.

Keywords: Vedic Mathematics, Urdhva Tiryakbhayam, VLSI Design, High-Speed Multiplier, Verilog HDL

Downloads: | DOI: 10.17148/IJARCCE.2026.15119