A Built-In Self Test By Enhanced Faults Coverage with Microcode Optimization for Embedded Memory

Abstract: System-on-chip (SoC) designs are moving from logic dominant chips to memory dominant chips to be able to meet future application requirements. Embedded memory density and area on-chip is increasing day by day. In order to achieve good memory yield, an at-speed test technique such as built-in self test (BIST) must be implemented to test these embedded memories. Memory Built-in Self Test (MBIST) is the popular approach to test embedded memories. MBIST usually use the deterministic pattern such as MARCH test algorithm to test memories. In MARCH test algorithm, the patterns are generated according to specified predetermined values. The existing March algorithms consist of as many as four or seven operations per March element. Therefore, it is essential to define new test algorithms which fulfill the need of detecting new faults. A new March BLC tests having number of operations per element according to the today‟s growing needs of embedded memory testing with enhanced fault using Verilog HDL as a primary language and used Modelsim SE 6.5 f as simulation tool.

Keywords: Memory Built-In Self Test (MBIST), Embedded memory fault, Hardware Descriptive Language (HDL)