Design and Implementation of PCM Decommutator On A Single FPGA

Abstract: After frame synchronization, individual measurands are identified according to the frame location. The decommutator identifies and extracts embedded asynchronous data stream (EADS) words. Thus PCM Decommutator is a very crucial subsystem in the satellite data acquisition unit of satellite ground station. A PCM decommutator is designed and implemented on a Stratix FPGA. The Hardware design comprises of four modules. a) Decommutator b) FPGA on chip memory bank c) Data storage on external FIFO banks d) PCI-X Master IP core integrated on the same FPGA. Decommutator will identify and separate the individual parameters from the incoming satellite PCM stream. M4k memory of the Stratix is used to develop a FPGA on chip Memory module to temporarily store small volume of the decommutated data before sending it to a large FIFO on the board. Altera 64bit Master IP core is integrated into the same FPGA to interface the stored data to a higher end server. A software program is written in Visual C++ to read the data from FIFO and store in the server RAID. The validation of the modules is done with an inbuilt data simulator.

Keywords: Frame Synchronization, Decommutation, Onchip RAM, PCI Master Core