Design and Physical Verification of Low Power 4words X 4bits SRAM System using an Adaptive Voltage Level (AVL) Technique

Abstract: The scaling of CMOS technology has significant impacts on SRAM cell random fluctuation of electrical characteristics and substantial leakage currents. Reduction of leakage current is very important for low power applications. This provides the motivation to the design of low leakage SRAM cells, because these high leakage currents are becoming a major contributor to total power dissipation of CMOS circuits. Memory leakage suppression is critically important for the success of power-efficient designs, especially for ultra- low power applications. In order to achieve low power design there many techniques are presented earlier like Multiple Vdd supply, Multiple Vth technique, SVL scheme, but these techniques will reduce only subthreshold leakages in SRAM cell and leaves gate leakage as remains. The proposed adaptive voltage level (AVL) circuit is added to Asymmetric 10T-SRAM cell, to reduce the sub-threshold leakage and as well as gate leakage, which controls the effective voltage across the SRAM cell in inactive mode. And Simulations are performed with 90nm CMOS technology process file and the leakage power and leakage currents of all the cells are measured and compared. Simulation results revealed that there is a significant reduction in leakage power for this proposed cell with the AVL circuit.

Keywords: AVL scheme, Gate leakage, Low power, Subthreshold leakage, SRAM cell.