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Design and Physical Verification of Low Power 4words X 4bits SRAM System using an Adaptive Voltage Level (AVL) Technique
KUMARASWAMY N, MAHESH B NELAGAR PG Student, VLSI Design and Embedded systems, PG Study centre VTU, Belgaum, India Asst. professor, VLSI Design and Embedded systems, PG Study centre VTU, Belgaum, India
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This work is licensed under a Creative Commons Attribution 4.0 International License.How to Cite:
[1] KUMARASWAMY N, MAHESH B NELAGAR PG Student, VLSI Design and Embedded systems, PG Study centre VTU, Belgaum, India Asst. professor, VLSI Design and Embedded systems, PG Study centre VTU, Belgaum, India, βDesign and Physical Verification of Low Power 4words X 4bits SRAM System using an Adaptive Voltage Level (AVL) Technique,β International Journal of Advanced Research in Computer and Communication Engineering (IJARCCE)