Design of a Low Power Clock Multi Band Network for Supplying the Multi Clock Domain Networks

Abstract: when working with IC’s most of the power will be consumed for making the IC in to active working state. This depends on the clock distribution networks. Because the clock signals have the high switching activity. Normally for a multi clock domain networks the power consumed by the clock signals is too high to lower this we generally use multiple PLL’s, in this project we aim for developing a low power single clock multiband network which will supply for the multi clock domain network. This design is highly useful for communication applications. A low power clock model network is designed for LAN using pulse-swallow topology and the design is modelled using Verilog simulated using Model sim and implemented in Xilinx.

Keywords: Clock signals, Buffers, Multi band networks, Counters, AC-TSPC