Design of Multiplier Using Regular Partial Products

Abstract: The conventional Modified Booth Encoding (MBE) generates n/2+1 rows instead of n/2 rows and also irregular partial product array because of the extra partial product bit at the LSB position of each partial product row. In this brief, a simple approach is proposed to generate n/2 partial product rows along with a regular partial product arrays and negligible overhead, thereby lowering the complexity of partial product and reducing the area and power of MBE multipliers. The proposed approach can also be utilized to regularize the partial product array of MBE multipliers along with the issue of disposal of the negative partial products efficiently by computing the 2's complement thereby avoiding the additional adder for adding 1 and generation of long carry chain. The proposed mechanism also continues to support the concept of reducing the partial product from n/2 +1 partial products achieved via modified booths algorithm to n/2.In this direct two's complement method has been used to reduce partial product rows from n/2+1 to n/2.Implementation results demonstrate that the proposed MBE multipliers with a regular partial product array really achieve significant improvement in area and power consumption when compared with conventional MBE multipliers. Here different multipliers have been designed and compared. These multipliers have been designed with the help of Verilog, simulated on Modelsim SE 6.3f and synthesized on Xilinx FPGA Spartan 3E xc3s500E, that helps in comparing their area, power and delay.

Keywords: DSP, MBE, PP, VLSI