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International Journal of Advanced Research in Computer and Communication Engineering
International Journal of Advanced Research in Computer and Communication Engineering A monthly Peer-reviewed & Refereed journal
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Design of Resource Efficient FIR Filter Structure Using Adders and Multiplier

P.C.FRANKLIN, M.RAMYA, R.NAGARAJAN, T.M. MINI PRIYA, M.BALAMURUGAN PG Scholar, Embedded System Technologies, S.A Engineering College, Chennai, India Lecturer, Electronics and Communication Engineering, S.A Engineering College, Chennai, India PG Scholar, Embedded System Technologies, S.A Engineering College, Chennai, India PG Scholar, Embedded System Technologies, S.A Engineering College, Chennai, India PG Scholar, Embedded System Technologies, S.A Engineering College, Chennai, India

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Abstract: This paper presents high speed digital Finite Impulse Response (FIR) filter relying on Wallace tree multiplier and Carry Select Adder (CSLA). Adder has three architectures such as basic CSLA using RCA (Ripple Carry Adder), CSLA using BEC (Binary to Excess-1 Converter) and CSLA using D-latch. In this paper we propose 4- tap FIR Filter architecture using 16-bit CSLA using D-latch and 8-bit Wallace tree multiplier. These multipliers and adders are used for high speed operation of digital FIR filter.

Keywords: CSLA, RCA, BEC, D-latch and Wallace tree multiplier.

How to Cite:

[1] P.C.FRANKLIN, M.RAMYA, R.NAGARAJAN, T.M. MINI PRIYA, M.BALAMURUGAN PG Scholar, Embedded System Technologies, S.A Engineering College, Chennai, India Lecturer, Electronics and Communication Engineering, S.A Engineering College, Chennai, India PG Scholar, Embedded System Technologies, S.A Engineering College, Chennai, India PG Scholar, Embedded System Technologies, S.A Engineering College, Chennai, India PG Scholar, Embedded System Technologies, S.A Engineering College, Chennai, India, β€œDesign of Resource Efficient FIR Filter Structure Using Adders and Multiplier,” International Journal of Advanced Research in Computer and Communication Engineering (IJARCCE)

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