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International Journal of Advanced Research in Computer and Communication Engineering A monthly Peer-reviewed & Refereed journal
ISSN Online 2278-1021ISSN Print 2319-5940Since 2012
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← Back to VOLUME 5, ISSUE 1, JANUARY 2016

Design, Simulation & Optimization of 45nm NMOS Transistor

Ms.Nitin Sachdeva, Dr. Munish Vashishath

DOI: 10.17148/IJARCCE.2016.5167

Abstract: This paper focuses on the result of process & device simulation using SILVACO TCAD tools to develop and optimize 45nm NMOS electrical characteristics using Gaussian doping profile. Fabrication process of transistor was performed in Athena while electrical characterisation of device was performed by ATLAS simulator. The analysis focussed on ID-VGS curve, IG-VDS curve, threshold voltage, ON and OFF currents, DIBL estimation, dependency of threshold voltage on various parameters like gate oxide thickness, VTH adjust implant doping concentration and Halo implant doping concentration . From the simulation result, optimum solution of threshold voltage of 0.095V has been achieved.



Keywords: MOSFET, Silvaco, threshold voltage, DIBL, Athena.

How to Cite:

[1] Ms.Nitin Sachdeva, Dr. Munish Vashishath, “Design, Simulation & Optimization of 45nm NMOS Transistor,” International Journal of Advanced Research in Computer and Communication Engineering (IJARCCE), DOI: 10.17148/IJARCCE.2016.5167