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Effective Power Optimization Of Cms Scheme
PRIYADHARSINI R, MR. MAHESHKUMAR H PG Scholar, Department of PG, Electrical sciences, P.A.College of Engineering and Technology, Coimbatore, TamilNadu, India Assistant Professor, Department of PG- Electrical sciences, P.A.College of Engineering and Technology, Coimbatore, TamilNadu, India
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Abstract: Continuous scaling down of the transistor size causes the delay of local wires to decreases while delay of global wires remains the same. The current mode signaling (CMS) with effective bias circuit produce low power consumption over long on chip interconnect. This paper deals with variation tolerance with dynamic overdriving that produce less power consumption and proposed smart bias that increases the signal integrity through long distance communication. This proposed Smart bias is sensitive to both inter-die and intra-die variation. The CMS scheme and the proposed scheme is tested using 0.18um technology.
Keywords: Dynamic Overdriving, On-Chip Interconnect, Current Mode Signaling (CMS), Smart Bias
Keywords: Dynamic Overdriving, On-Chip Interconnect, Current Mode Signaling (CMS), Smart Bias
How to Cite:
[1] PRIYADHARSINI R, MR. MAHESHKUMAR H PG Scholar, Department of PG, Electrical sciences, P.A.College of Engineering and Technology, Coimbatore, TamilNadu, India Assistant Professor, Department of PG- Electrical sciences, P.A.College of Engineering and Technology, Coimbatore, TamilNadu, India, βEffective Power Optimization Of Cms Scheme,β International Journal of Advanced Research in Computer and Communication Engineering (IJARCCE)
This work is licensed under a Creative Commons Attribution 4.0 International License.