FPGA Implementation of FIR based Decimation Filter Structure for WiMAX Application

Abstract: This paper presents the implementation of two stage FIR (Finite Impulse Response) decimation filter using system generator and it is compared with single stage implementation of FIR filter for WiMAX Application. FIR filter with decimation factor M is subdivided into two decimation factors M1 and M2. The two different FIR filters are designed with different coefficient values and different sampling rate and cascaded instead of single stage FIR filter. The prototype is designed with MATLAB Simulink model and it is converted to VHDL code using Xilinx system generator. Prototype is implemented in Virtex V- FPGA kit and simulation results and device utilization reports are generated and tabulated. The result shows that the two stage FIR filter utilizes less LUT‟s and consumes less power than the single stage FIR filter. This low power implementation of two stage FIR filter may be used as a decimation filter in WiMAX application.

Keywords: Decimation, FIR – Finite Impulse Response Filter, SRC- Sampling Rate Conversion, DDC – Digital Down Converter, FPGA – Field Programmable Gate Array