Implementation of MESI Protocol Using Verilog

Abstract: Multiprocessor system is a system which contains two or more processors working simultaneously and sharing the same memory. Nowadays multiprocessors are being widely used due to their high throughput and reliability. It is important to maintain data consistency in multiprocessor system as different processors may communicate and share the data with each other. In multiprocessor systems caching plays a very important role. Cache coherence is a major issue in multiprocessor systems. In this paper we have designed three direct-mapped caches and to maintain cache coherence and data consistency among the processors we have used the MESI protocol. The MESI protocol is invalidation based cache coherence protocol. In this protocol each cache block can be in one of four states i.e., Modified, Exclusive, Shared and Invalid. In this protocol, whenever a processor writes into the local cache, all copies of it in other processors are invalidated in order to maintain data consistency and cache coherence. The cache design is simulated and synthesized using Xilinx ISE 14.7 Simulator and XST Synthesizer.

Keywords: Cache Coherence, Direct-mapped Cache, MESI, Xilinx.