Method for a Fast-Lock Low-Jitter Delay-Locked Loop using a Dual Charge Pump and Lock Control Circuit

NILESH D. PATEL; AMISHA P. NAIK; RONAK J. PATEL Research Scholar; Institute of Technology; Nirma University; Ahmedabad Associate Professor; Institute of Technology; Nirma University; Ahmedabad PG Student; CIT; Changa

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Method for a Fast-Lock Low-Jitter Delay-Locked Loop using a Dual Charge Pump and Lock Control Circuit

NILESH D. PATEL, AMISHA P. NAIK, RONAK J. PATEL Research Scholar, Institute of Technology, Nirma University, Ahmedabad Associate Professor, Institute of Technology, Nirma University, Ahmedabad PG Student, CIT, Changa

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[1] NILESH D. PATEL, AMISHA P. NAIK, RONAK J. PATEL Research Scholar, Institute of Technology, Nirma University, Ahmedabad Associate Professor, Institute of Technology, Nirma University, Ahmedabad PG Student, CIT, Changa, “Method for a Fast-Lock Low-Jitter Delay-Locked Loop using a Dual Charge Pump and Lock Control Circuit,” International Journal of Advanced Research in Computer and Communication Engineering (IJARCCE)