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This work is licensed under a Creative Commons Attribution 4.0 International License.
Method for a Fast-Lock Low-Jitter Delay-Locked Loop using a Dual Charge Pump and Lock Control Circuit
NILESH D. PATEL, AMISHA P. NAIK, RONAK J. PATEL Research Scholar, Institute of Technology, Nirma University, Ahmedabad Associate Professor, Institute of Technology, Nirma University, Ahmedabad PG Student, CIT, Changa
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Abstract: Author has described a method for a fast-lock low-jitter delay-locked loop using a dual charge pump and lock control circuit. Benefits include improved functionality, improved performance, and improved cost effectiveness.
Keywords: Charge pump, Loop filter, Phase frequency detector (PFD), VCDL
Keywords: Charge pump, Loop filter, Phase frequency detector (PFD), VCDL
How to Cite:
[1] NILESH D. PATEL, AMISHA P. NAIK, RONAK J. PATEL Research Scholar, Institute of Technology, Nirma University, Ahmedabad Associate Professor, Institute of Technology, Nirma University, Ahmedabad PG Student, CIT, Changa, βMethod for a Fast-Lock Low-Jitter Delay-Locked Loop using a Dual Charge Pump and Lock Control Circuit,β International Journal of Advanced Research in Computer and Communication Engineering (IJARCCE)
This work is licensed under a Creative Commons Attribution 4.0 International License.