Performance analysis of Effects of Parasitic Elements on the MOSFET Current–Voltage Model on its physical parameters

Abstract: This work we analyze the parametric estimation for MOSFET switching delay, leakage current reduction , power dissipation and variation of temperature effects due to the parasitic devices. One solution to the problem of ever- increasing leakage is to force a non-stack device to a stack of two devices without affecting the input load. The stacking of two off devices has significantly reduced sub-threshold leakage compared to a single off device. Logic gates after stack forcing will reduce leakage power, but incur a delay penalty, similar to replacing a low- Vt device with a high-Vt device in a dual-Vt design. Due to stacking of devices, the drive current of a forced-stack gate will be lower resulting in increased delay. Here we can design a full adder logic circuit using stack transistors.