Word serial architecture of CORDIC

Abstract: CORDIC is an acronym for Co-ordinate Rotation Digital Computers and was derived by Volder[1] in late 1950‟s for the purpose of calculating trigonometric functions. It is widely used in the computing of elementary functions and digital signal processing applications[4], particularly where large amounts of rotation operations are necessary.The original algorithm describes the rotation of 2-D vector which can be applied in applications such as DSP (for Fourier Transforms, Digital Filters)[10] computer graphics and Robotics.
CORDIC processing offers high computational rates making it attractive to applications such as computer graphics where a combination of scaling and rotations are required in real time. CORDIC is also attractive to Robotics[7] since the fundamental operation is co-ordinate transformation[2]. However it could be used for more computationally intensive processes such as motion planning [3]and collision detection.Array imaging [3]typically involves complex signal processing[8] which may require many computationally intensive matrix operations[8].
As intended by Jack E. Volder [1] the CORDIC Algorithm only performs shift and add operations and is therefore easy to implement and resource friendly. However, when implementing the CORDIC algorithm one can choose between various design methodologies and must balanced circuit complexity with respect to performance. It avoids the use of traditional multiplier and accumulator unit [MAC unit] which generally is the bottleneck for the faster systems.This paper attempts to explorer FPGA implementation of CORDIC algorithm using word serial architecture.

Keywords: CORDIC,FPGA,DSP,MAC