Abstract: The basic requirement of any Integrated Circuit is high speed and low power processing of the data signals to perform the desired execution. The minimization of feature size plays an important role in increasing the performance of integrated circuits. But the feature minimization inversely affects the percentage of leakage current when compared to the total current requirement of the circuit. So in this research we design single bit magnitude comparator & 3 input EXOR gate using conventional CMOS logic style as well as DCVSL style and then compared the output of both designs with some parameters. These parameters are power dissipation, delay and number of transistors used in the respective designs, and then concluded that which design yields best results. In CMOS circuits, as the technology scales down to nano scale, the sub-threshold leakage current increases with the decrease in the threshold voltage. So we need a technique to tackle the power dissipation problem in CMOS circuits do the analysis keeping parameters such as power consumption, delay, voltage & transistor count. First, there is the analysis between power consumption & delay, keeping the voltage constant at 1.8V. We here can see that circuit of the DCSVL structures produces better results in terms of power consumption by lowering its value. The circuit designed using DCVS Logic style is an attempt to further reduce the power dissipation with minimum delay.
Keywords: CMOS, 1-bit Magnitude comparator, EXOR gate, DCVSL, delay, transistor count, power dissipation.
| DOI: 10.17148/IJARCCE.2018.75557