Abstract: Approximate computing is a paradigm shift in energy-efficient systems design and operation, based on the idea that we are hindering computer systems’ efficiency by demanding too much accuracy from them. Interestingly, large number of application domains, such as DSP, statistics, and machine learning. Approximate computing is suited for efficient data processing and error resilient applications, such as signal and image processing, computer vision, machine learning, data mining etc. Approximate computing circuits are considered as a promising solution to reduce the power consumption in embedded data processing. This paper proposes an FPGA implementation for an approximate multiplier based on selective fractional part based truncation multiplier circuits. The performance of the proposed multiplier is evaluated by comparing the power consumption, the accuracy of computation, and the time delay with those of an approximate multiplier based on exact computation presented. The approximate design obtained energy efficient mode with acceptable accuracy. As compared to conventional direct truncation proposed model significantly influences the performance. Therefore, this novel energy efficient rounding based approximate multiplier architecture outperformed other competitive model.
Keywords: FPGA,DSP,Approximate Multiplier
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DOI:
10.17148/IJARCCE.2024.131219
