Abstract: This paper is motivated for the efficient high speed Vedic multiplier with implementation in FPGA. Recent and advanced Vedic multiplications of multipliers are implemented by using Urdhva tiryakbhyam multiplication technique is commonly used in different multiplier architectures. This multiplication algorithm is giving less delay and efficient power utilization with reduction of area. The 16x16 Vedic multiplier is synthesized in Xilinx and implemented in FPGA.
Keywords: Field Programmable Gate Array (FPGA), Vedic multiplier Technology
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DOI:
10.17148/IJARCCE.2019.8609
[1] Mr.T.Muruganantham, Mr.N.R.Nagarajan, Mr.S.Syed Husain, "A 16X16 High Speed Vedic Multiplier for Area and Power Reduction," International Journal of Advanced Research in Computer and Communication Engineering (IJARCCE), DOI: 10.17148/IJARCCE.2019.8609
