Abstract: In present work, a comparative analysis of conventional 6T, 7T and 8T SRAM cells has been performed using 180nm process design kit using Cadence Virtuoso. As the CMOS technology getting shifted in nanometer regime it faces a lot of challenges such as short channel effect and process variations. The SRAM parameters such as stability, power dissipation and delay of these considered cells have been investigated. It has been observed that write delay in 6T cell is improved by 2× and 0.14× as compared to 7T and 8T SRAM cells respectively. Furthermore, average read and writes power consumption of 7T SRAM cell found to be 1.2× and 0.98× less as compared to 6T and 8T SRAM cells respectively. Additionally, the 8T cell is having moderate write SNM i. e 32% more than 6T cell but 9% less than 7T cell.
Keywords: SRAM, delay, power dissipation, static noise margin, T (transistor).
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DOI:
10.17148/IJARCCE.2022.11906
