Abstract: Analog to Digital Converter (ADC) is a most useful devices for extracting the digital signals from the analog signals. The processing speed of successive approximation type ADC is depending highly on the operations of the comparators, which is the important parts of structure. In day todays digital ultratech world, low power consumption & speed are the major factor that need to be considered. High speed comparator is much affective to the overall performance of ADC. In order to design a better comparator that will function optimally in real environments without changing its characteristic. Factors like propagation delay, power dessipation, and voltage supply must be taken into account when designing a low power and voltage comparator. These factors are represented in this paper. This essay compares several comparators, including complex circuit, length of design, CMOS technology, and others. A 45nm-based comparator's design, followed by a Cadence Virtuoso simulation.

Keywords: Analog-to-Digital-Converter (ADC), Digital-to-Analog-Converter (DAC), Successive Approximation Register (SAR), Low Power, High speed clock frequency, Conventional Dynamic.

PDF | DOI: 10.17148/IJARCCE.2023.12413

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