International Journal of Advanced Research in Computer and Communication Engineering

A monthly peer-reviewed online and print journal

ISSN Online 2278-1021
ISSN Print 2319-5940

Since 2012

Abstract: Data driven gating is causing area and power overheads that must be considered. To reduce the overhead, it is proposed to group several FFs to be driven by the same clock signal, generated by bring the enabling signals of the individual FFs. This may however, lower the disabling effectiveness. In a recent paper, a model for data-driven gating is developed based on the toggling activity of the constituent FFs. The optimal fan-out of a clock gate yielding maximal power savings is derived based on the average toggling statistics of the individual FFs, process technology, and cell library in use. Data driven clock gating is a popular technique used in many synchronous circuits for reducing dynamic power dissipation. When a logic unit is clock, its underlying sequential elements receive the clock signal regardless of whether they will toggle in the next cycle. In this flip-flops are grouped so that they share a common clock enabling signal to reduce the hardware overhead and power consumption.

Keywords: Data Driven, Logic Gates, Flip-Flops, Clock Gating, AND Clock Gating


PDF | DOI: 10.17148/IJARCCE.2019.81103

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