Abstract: Reversible or information lossless gates have applications in nano-technology, digital signal processing (DSP) and in communication The power consumption is one of the biggest challenging issues for designing of VLSI circuits within the advanced technology. The reversible logic is one among the best approaches for low power application The main objective of this paper is to design and implementation of a magnitude comparator using reversible logic approaches. In this paper a 16-bit and 32-bit magnitude comparator are implemented with using reversible logic gates. The simulation of 16-bit and 32-bit magnitude comparator is carried out using Verilog HDL coding in Xilinx Software. Simulation results provide significant improvement in power consumption for 16-bit and 32-bit magnitude comparator using the proposed reversible logic gates method. Therefore, the proposed scheme can provide a significant improvement in comparator circuit in chips for future generation of VLSI blocks.
Keywords: Reversible, Verilog HDL, Xilinx, BJN gate, Power consumption.
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DOI:
10.17148/IJARCCE.2024.13730
