Abstract: As the Technology changes testing of a integrated circuits should be simpler, easier and faster to complete the process, according to the Design For Testability (DFT) process, testing of the integrated circuit becomes complex depending upon the number of flip flops present in the design. To make the testing simpler we are going to compression up to 20x and 25x depending upon the input configuration. It will be simple to find the input/output test channels for test coverage. In this paper we have defined to make test time and test data volume very simple and easier for multi users at different input. Scan insertion and compression can be done easily but EDT Compression is a tool used to make for multi configuration depending on the multi-input and multi output configurations. In this process of testing the integrated circuits and ATPG (Automatic Test Pattern Generation) setup can be done for the multi configuration. Experiments are done based on the multi-channel configuration for multi users at different compression Ratios, Serial and parallel Patterns can be generated according to configuration level
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DOI:
10.17148/IJARCCE.2022.11109
