Abstract: This brief presents an approach for a technique to systematically tradeoff accuracy in exchange for area, power, and delay savings in digital circuits is proposed: gate-level pruning (GLP). The methodology is first demonstrated on adders, achieving up to 78% energy-delay-area reduction for relative error. It is then detailed how this methodology can be applied on a more complex system composed of a multitude of arithmetic blocks and memory: the discrete cosine transform(DCT), which is a key building block for image and video processing applications. Even though arithmetic circuits represent less than the entire DCT area, it is shown that the GLP technique can lead to energy-delay-area savings over the entire system for a reasonable image quality loss. This GLP approach can be Implemented using Verilog HDL and Simulated by Modelsim 6.4 c. Finally it’s synthesized by Xilinx tool.
Keywords: DCT, Verilog HDL, Xilinx tool.
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DOI:
10.17148/IJARCCE.2024.131217
