Abstract: As the demand for energy-efficient electronic devices continues to grow, the focus on low-power memory designs becomes paramount. Our Project presents a comprehensive study on the design and verification of low-power SRAM memory cells, addressing the critical need for energy-efficient memory solutions in contemporary electronic systems. The primary objective is to optimize SRAM cells for reduced power consumption while maintaining satisfactory performance and reliability. The basic 6T Static Random Access memory (SRAM) cell experience from relatively high static and total power loss problem, to solve this 4T SRAM cell is designed. As the technology is shrinking, a significant amount of attention is being paid on the design of high stability Static Random Access (SRAM) cells in terms of static Noise Margin (SNM) for different levels of cache memories. This project presents a qualitative design of 4T Static Random Memory Access cell in terms of Read cell current, Write time, Static Noise Margin (Read and Hold), Write Noise Margin in 45nm and 90nm CMOS technology.
Keywords: SRAM, CMOS, EEPROM, PMO, NMO, PMI.
|
DOI:
10.17148/IJARCCE.2025.14677
