Abstract: Design implementation of SRAM cell based on low power consumption technique. In the field of VLSI research in electronic circuitry and memory is the basic demand of most electronic devices. RAM is used as main memory for small value devices that do not have a cache. Therefore, the construction of memory using an optimized SRAM cell in terms of process parameters, i.e. power consumption, quantity, area and delay, is a domain of VLSI research in electronic circuitry and memory. Critical analysis and the same are present circuit like 10T-SRAM in a functional way high power used but the SRAM-10T was found to have better performance in terms of speed but has a higher access time .These memory components are designed specifically using a CMOS transistor. They talk about CMOS power, the area and speed of each transistor is a big deal, but our proposed design knows are three types of design circuit things like LPCT-RD, LPCT-WD and LPCT. Engineers and researchers are still working on these questions. Various methods have been used to reduce power leakage within the designed circuit. As a circuit analysis processing, using memory capacity in design SRAM cell circuit is reduced power and also performance improves memory works like read, write and power saving better as compare existing circuit 10T. It is using simulation micro wind tool and also computing power, when compared to the results obtained in mode CMOS with micro wind tool. The 10T SRAM bit cell are not reduced power and performance not better the designed 10T SRAM bit cell showed in research study, poor performance, more power utilize of the 10T SRAM bit cell. Proposed design read times, write times access to LPCT-SRAM bit cell intended to increase and decrease volume but low power utilize and other side existing circuit 10T-SRAM model components are low performance. Finally our proposed circuits (LPCT) are reliable and efficient.
Keywords: VLSI, Memory, SRAM, DRAM, Power Consumption, Power Reduction, Power Dissipation, CMOS Technology, Read Delay, Write Delay LPCT.
| DOI: 10.17148/IJARCCE.2021.101243