Abstract: Full adder is a digital logic circuit that implements addition of binary numbers. The circuit of full adder forms a basic component of ALU (Arithmetic Logic Unit) in Microcontrollers and Microprocessors. They are used in concepts like Fast Fourier Transform in DSPs.
In order to generate memory addresses inside a computer and to make the Program Counter point to next instruction, the ALU makes use of full adders. Full adders are a part of Graphics Processing Unit for graphics related applications.
The objective of this project is to analyze the 16T low power CPTL full adder and optimize its power dissipation and propagation delay by simulating the circuit in 45 nm and 32 nm processes. By implementing designs across successive process generations, 2-dimensional design space is explored for low power and high performance. The performance of full adder is validated across a range of frequencies upto 1.25 GHz. The SPICE based simulations are carried out using
LTspice
Keywords: VLSI, CMOS, CPTL,Full adder,ALU, Power, Delay.
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DOI:
10.17148/IJARCCE.2022.11908
